View 11257-811_378574.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
1.0
* * *
Features
2.0
Description
Generates up to eighteen low-skew, non-inverting clocks from one clock input Supports up to four SDRAM DIMMs 2 Uses either I CTM-bus or SMBus serial interface with Read and Write capability for individual clock output control Output enable pin tristates all clock outputs to facilitate board testing Clock outputs skew-matched to less than 250ps Less than 5ns propagation delay Output impedance: 17 at 0.5VDD Serial interface I/O meet I C specifications; all other I/O are LVTTL/LVCMOS-compatible Five differerent pin configurations available:
* * * * FS6050: 18 clock outputs in a 48-pin SSOP FS6051: 10 clock outputs in a 28-pin SOIC, SSOP FS6053: 13 clock outputs in a 28-pin SOIC FS6054: 14 clock outputs in a 28-pin SOIC
2
* * * * *
*
The FS6050 family of CMOS clock fanout buffer ICs are designed for high-speed motherboard applications, such (R) as Intel Pentium II PC100-based systems with 100MHz SDRAM. Up to eighteen buffered, non-inverting clock outputs are fanned-out from one clock input. Individual clocks are skew matched to less than 250ps at 100MHz. Multiple power and ground supplies reduce the effects of supply noise on device performance. 2 Under I C-bus control, individual clock outputs may be turned on or off. An active-low output enable is available to force all the clock outputs to a tristate level for system testing.
Figure 2: Pin Configuration (FS6050)
SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_11 SDRAM_10 SDRAM_17 SDRAM_9 SDRAM_8 (reserved) (reserved) VDD VSS VSS
27
VSS_I2C
26 23
VDD
VDD
VDD
VDD
VSS
VSS
VSS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Figure 1: Block Diagram (FS6050)
10
FS6050
11 12 13 14 15 16 17 18 19 20 21 22
VDD
(reserved)
(reserved)
SDRAM_3
SDRAM_4
SDRAM_5
SDRAM_6
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_7
SDRAM_16
VDD
VDD
VDD
VDD
CLK_IN
VDD
VDD_I2C
VSS
VSS
VSS
VSS
VSS
SDRAM_(0:1)
VDD_I2C VSS VDD
SDA Serial Interface SCL
VSS_I2C 18
SDRAM_(2:3)
VSS VDD
48-pin SSOP
SDRAM_(4:5)
VSS VDD
SDRAM_(6:7) CLK_IN
VSS VDD
Figure 3: Pin Configuration (FS6051)
SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_17 VDD VDD VDD VSS VSS VSS_I2C VSS OE SCL
SDRAM_(8:9)
VSS VDD
28
27
26
25
24
23
22
21
20
19
18
17
16
VSS VDD
SDRAM_(12:13)
VSS VDD
FS6051
10 11 12 13 14 1 2 3 4 5 6 7 8 9
SDRAM_(14:15)
VSS VDD
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_16
VDD_I2C
VDD
VDD
CLK_IN
VDD
SDRAM_16 OE
VSS VDD
SDRAM_17
VSS
28-pin SOIC, SSOP
FS6050
Additional pin configurations are noted on Page 2.
,62
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a licensed trademark of Philips Electronics, N.V. American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 4.5.99
SDA
VSS
VSS
VSS
15
SDRAM_(10:11)
SDA
24
1
2
3
4
5
6
7
8
9
25
SCL
OE
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X T
April 1999
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN (FS6050) 11 25 24 4 5 8 9 13 14 17 18 31 32 35 36 40 41 44 45 21 28 38 3, 7, 12, 16, 20, 29, 33, 37, 42, 46 23 6, 10, 15, 19, 22, 27, 30, 34, 39, 43 26 1, 2, 47, 48
PIN (FS6051) 9 15 14 2 3 6 7 22 23 26 27 11 18 20 1, 5, 10, 19, 24, 28 13 4, 8, 12, 17, 21, 25 16 -
PIN (FS6053) 9 15 14 2 3 6 7 10 11 18 19 22 23 26 27 12 1, 5, 20, 24, 28 13 4, 8, 17, 21, 25 16 -
PIN (FS6054) 9 15 14 2 3 6 7 10 11 18 19 22 23 26 27 12 17 20 1, 5, 24, 28 13 4, 8, 21, 25 16 -
TYPE DI DIU DIUO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DIU P P P P -
NAME CLK_IN SCL SDA SDRAM_0 SDRAM_1 SDRAM_2 SDRAM_3 SDRAM_4 SDRAM_5 SDRAM_6 SDRAM_7 SDRAM_8 SDRAM_9 SDRAM_10 SDRAM_11 SDRAM_12 SDRAM_13 SDRAM_14 SDRAM_15 SDRAM_16 SDRAM_17 OE VDD VDD_I2C VSS VSS_I2C (reserved)
DESCRIPTION Clock input for SDRAM clock outputs Serial clock input Serial data input/output
SDRAM clock outputs (Byte 0)
SDRAM clock outputs (Byte 1)
SDRAM feedback clock outputs (Byte 2) Output enable tristates all clock outputs when low 3.3V 5% power supply for SDRAM clock buffers 3.3V 5% power supply for serial communications Ground for SDRAM clock buffers Ground for serial communications Reserved
Figure 4: Pin Configuration (FS6053)
SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_9 SDRAM_8 VSS_I2C VDD VDD VDD VSS VSS VSS SCL
Figure 5: Pin Configuration (FS6054)
SDRAM_13 SDRAM_15 SDRAM_14 SDRAM_12 SDRAM_9 SDRAM_17
17
SDRAM_8
VDD
VDD
VSS
VSS
VSS_I2C
16 13
28
27
26
25
24
23
22
21
20
OE
19
18
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FS6053
10 11 12 13 14
1 2 3 4 5
FS6054
10 11 12 14 6 7 8 9
1
2
3
4
5
6
7
8
9
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_6
SDRAM_7
SDRAM_16
VDD_I2C
VDD
VDD
CLK_IN
VSS
SDRAM_16
SDRAM_3
SDRAM_6
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_7
CLK_IN
VDD
VDD
VDD_I2C
SDA
SDA
VSS
VSS
VSS
15
SCL
4.5.99
,62
2
)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
3.0
Programming Information
3.2
Register Programming
Table 2: Clock Enable
CONTROL INPUTS OE 0 1 CLOCK OUTPUTS (MHz) SDRAM_0:17 tristate CLK_IN
A logic-one written to a valid bit location turns on the assigned output clock. Likewise, a logic-zero written to a valid bit location turns off the assigned output clock. Any unused or reserved register bits should be cleared to zero. Serial bits are written to this device in the order shown in Table 3.
Table 3: Register Summary
3.1
Power-Up Initialization
SERIAL BIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
DATA BYTE
CLOCK OUTPUT SDRAM_7 SDRAM_6 SDRAM_5
All outputs are enabled and active upon power-up, and all output control register bits are initialized to one. The outputs must be configured at power-up and are not expected to be configured during normal operation. Inactive outputs are held low and are disabled from switching.
(MSB)
Byte 0 SDRAM Control Register 0
SDRAM_4 SDRAM_3 SDRAM_2 SDRAM_1
3.1.1 Unused Outputs Outputs that are not used in versions of this device with a reduced pinout are still operational internally. To reduce power dissipation and crosstalk effects from the unloaded outputs, it is recommended that these outputs be shut off via the Control Registers.
(LSB) (MSB)
SDRAM_0 SDRAM_15 SDRAM_14 SDRAM_13
Byte 1 SDRAM Control Register 1
SDRAM_12 SDRAM_11 SDRAM_10 SDRAM_9
(LSB) (MSB)
SDRAM_8 SDRAM_17 SDRAM_16 Reserved
Byte 2 SDRAM Control Register 2
Reserved Reserved Reserved Reserved
(LSB)
Reserved
4.5.99
,62
3
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X T
April 1999
Table 4: Byte 0 - SDRAM Control Register 0
REGISTER BIT 7 6 5 4 3 2 1 0 CLOCK OUTPUT SDRAM_7 SDRAM_6 SDRAM_5 SDRAM_4 SDRAM_3 SDRAM_2 SDRAM_1 SDRAM_0 DESCRIPTION On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) OUTPUT PIN (FS6050) Pin 18 Pin 17 Pin 14 Pin 13 Pin 9 Pin 8 Pin 5 Pin 4 OUTPUT PIN (FS6051) Pin 7 Pin 6 Pin 3 Pin 2 OUTPUT PIN (FS6053) Pin 11 Pin 10 Pin 7 Pin 6 Pin 3 Pin 2 OUTPUT PIN (FS6054) Pin 11 Pin 10 Pin 7 Pin 6 Pin 3 Pin 2
Table 5: Byte 1 - SDRAM Control Register 1
REGISTER BIT 15 14 13 12 11 10 9 8 CLOCK OUTPUT SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_11 SDRAM_10 SDRAM_9 SDRAM_8 DESCRIPTION On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) On (1) / Off (0) OUTPUT PIN (FS6050) Pin 45 Pin 44 Pin 41 Pin 40 Pin 36 Pin 35 Pin 32 Pin 31 OUTPUT PIN (FS6051) Pin 27 Pin 26 Pin 23 Pin 22 OUTPUT PIN (FS6053) Pin 27 Pin 26 Pin 23 Pin 22 Pin 19 Pin 18 OUTPUT PIN (FS6054) Pin 27 Pin 26 Pin 23 Pin 22 Pin 19 Pin 18
Table 6: Byte 2 - SDRAM Control Register 2
REGISTER BIT 23 22 21 20 19 18 17 16 CLOCK OUTPUT SDRAM_17 SDRAM_16 DESCRIPTION On (1) / Off (0) On (1) / Off (0) OUTPUT PIN (FS6050) Pin 28 Pin 21 OUTPUT PIN (FS6051) Pin 18 Pin 11 OUTPUT PIN (FS6053) Pin 12 OUTPUT PIN (FS6054) Pin 17 Pin 12 -
Reserved (set to 0) Reserved (set to 0) Reserved (set to 0) Reserved (set to 0) Reserved (set to 0) Reserved (set to 0)
4.5.99
,62
4
)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
4.0
Dual Serial Interface Control
This integrated circuit is a read/write slave device that 2 supports both the Inter IC Bus (I C-bus) and the System Management Bus (SMBus) two-wire serial interface protocols. The unique device address that is written to the device determines whether the part expects to receive 2 SMBus commands or I C commands. Since SMBus is 2 derived from the I C-bus, the protocol for both bus types is very similar. In general, the bus has to be controlled by a master device that generates the serial clock SCL, controls bus access, and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. Bus logic levels and timing parameters noted herein fol2 low I C-bus convention. Logic levels are based on a percentage of VDD. A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).
4.1.4 Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the data registers are filled will overflow from the last register into the first register, then the second, and so on, in a first-in, first-overwritten fashion. 4.1.5 Acknowledge When addressed, the receiving device is required to generate an Acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the Acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to allow the master to generate a STOP condition.
4.1
Bus Conditions
Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line when the clock line is high is interpreted by the device as a START or STOP 2 condition. Both I C-bus and SMBus protocols define the following conditions on the bus. Refer to Figure 12: Bus Timing Data for more information.
4.2
Bus Operation and Commands
4.1.1 Not Busy Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. 4.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. 4.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition.
All programmable registers can be accessed via the bidirectional two wire digital interface. The device accepts the Random Register Read/Write and the Sequential 2 Register Read/Write I C commands. The device also supports the Block Read/Write SMBus commands.
4.2.1 I2C-bus and SMBus Device Addressing After generating a START condition, the bus master broadcasts a seven-bit device address followed by a R/W 2 bit. Note that every device on an I C-bus or SMBus must have a unique address to avoid bus conflicts. For an SMBus interface, the address of the device is:
A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1
4.5.99
,62
5
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X T
April 1999 For an I C-bus interface, the device can support two de2 vice addresses to permit multiple devices on one I C-bus. The A2 address bit is ignored and can be set to either a one or a zero. 2 Therefore, for an I C-bus interface the device address is:
A6 1 A5 0 A4 1 A3 1 A2 X A1 0 A0 0
2
4.2.2
I2C-bus: Random Register Write Procedure Random write operations, as shown in Figure 6, allow the master to directly write to any register. To initiate a write procedure, the R/W 2 bit that is transmitted after the seven-bit I C device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. If either a STOP or a repeated START condition occurs during a Register Write, the data that has been transferred is ignored.
4.2.4 I2C-bus: Sequential Register Write Procedure Sequential write operations, as shown in Figure 8, allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the Random Register Write if several registers must be written. To initiate a write procedure, the R/W bit that is transmit2 ted after the seven-bit I C device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write data up to the last addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a Sequential Register Write. 4.2.5 I2C-bus: Sequential Register Read Procedure Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure, as shown in Figure 9, is more efficient than the Random Register Read if several registers must be read from. To perform a read procedure, the R/W bit that is trans2 mitted after the seven-bit I C address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition.
4.5.99
4.2.3 I2C-bus: Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, as shown in Figure 7, the R/W bit that is transmitted after the 2 seven-bit I C address is a logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition.
,62
6
)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
Figure 6: Random Register Write Procedure (I2C-bus)
S DEVICE ADDRESS WA REGISTER ADDRESS A DATA AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
Data Acknowledge STOP Condition Acknowledge From device to bus host
Figure 7: Random Register Read Procedure (I2C-bus)
S DEVICE ADDRESS WA REGISTER ADDRESS AS DEVICE ADDRESS RA DATA AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command STOP Condition NO Acknowledge
Figure 8: Sequential Register Write Procedure (I2C-bus)
S DEVICE ADDRESS WA REGISTER ADDRESS A DATA A DATA A DATA AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
Data Acknowledge
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
From device to bus host
Figure 9: Sequential Register Read Procedure (I2C-bus)
S DEVICE ADDRESS WA REGISTER ADDRESS AS DEVICE ADDRESS RA DATA A DATA AP
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Data Acknowledge READ Command Acknowledge
Data NO Acknowledge STOP Command
4.5.99
,62
7
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X T
April 1999
SMBus: Block Write The Block Write command permits the master to write several bytes of data to sequential registers, starting by default at Register 0. The Block Write command, as noted in Figure 10, begins with the seven-bit SMBus device address followed by a logiclow R/W bit to begin a Write command. Following an acknowledge of the SMBus address and R/W bit by the slave device, a command code is written. It is defined that all eight bits of the command code must be zero (0). After the command code of zero and an acknowledge, the host then issues a byte count that describes the number of data bytes to be written. According to SMBus convention, the byte count should be a value between 0 and 32; however this slave device ignores the byte count value. Following an acknowledge of the byte count, data bytes may be written starting with Register 0 and incrementing sequentially. An acknowledge by the device between each byte of data must occur before the next data byte is sent.
4.2.6
SMBus
4.2.7 SMBus: Block Read The Block Read command, shown in Figure 11, permits the master to read several bytes of data from sequential
registers, starting by default at Register 0. To perform a Block Read procedure the R/W bit that is transmitted after the seven-bit SMBus address is a logic-low, as in the Block Write procedure. The write bit resets the register address pointer to zero. Following an acknowledge of the SMBus address and R/W bit by the slave device, a command code is written. It is defined that all eight bits of the command code must be zero (0). Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave SMBus address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then will expect a byte count value (which will be ignored). Following the byte count value, the device will take command of the bus and will transmit all the data beginning with Register 0. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. If the master does not want to receive all the data, the master can not acknowledge the last data byte and then can issue a STOP condition of the next clock.
Figure 10: Block Write (SMBus)
S DEVICE ADDRESS WA A BYTE COUNT = N A DATA BYTE 1 A DATA BYTE N AP
7-bit Receive Device Address START Command
Command Code Acknowledge WRITE Command From bus host to device
Byte Count
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
Acknowledge From device to bus host
Figure 11: Block Read (SMBus)
S DEVICE ADDRESS W A AS DEVICE ADDRESS RA BYTE COUNT = N A DATA BYTE 1 A DATA BYTE N AP
7-bit Receive Device Address START Command
Command Code Acknowledge WRITE Command From bus host to device
7-bit Receive Device Address Repeat START Acknowledge From device to bus host
Byte Count Acknowledge READ Command
Data Acknowledge Acknowledge
Data NO Acknowledge STOP Command
4.5.99
,62
8
)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
5.0
Electrical Specifications
Table 7: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability.
PARAMETER Supply Voltage, dc, Clock Buffers (VSS = ground) Supply Voltage, dc, Serial Communications Input Voltage, dc Output Voltage, dc Input Clamp Current, dc (VI < 0 or VI > VDD) Output Clamp Current, dc (VI < 0 or VI > VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL VDD VDD_I2C VI VO IIK IOK TS TA TJ
MIN. VSS-0.5 VSS-0.5 VSS-0.5 VSS-0.5 -50 -50 -65 -55
MAX. 7 7 VDD+0.5 VDD+0.5 50 50 150 125 125 260 2
UNITS V V V V mA mA C C C C kV
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
Table 8: Operating Conditions
PARAMETER Supply Voltage, Clock Buffers Supply Voltage, Serial Communications Ambient Operating Temperature Range Input Frequency Output Load Capacitance Serial Data Transfer Rate SYMBOL VDD VDD_I2C TA fCLK CL Standard mode 10 100 CONDITIONS/DESCRIPTION 3.3V 5% 3.3V 5% MIN. 3.135 3.135 0 0 TYP. 3.3 3.3 MAX. 3.465 3.465 70 133 30 400 UNITS V V C MHz pF kb/s
4.5.99
,62
9
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X T
April 1999
Table 9: DC Electrical Specifications
Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical. Negative currents indicate current flows out of the device.
PARAMETER Overall (FS6050) Supply Current, Dynamic, with Loaded Outputs Supply Current, Static
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDD IDDL
fCLK = 100MHz; VDD = 3.47V Outputs low; VDD = 3.47V
180 0.75
360 3
mA mA
Serial Communication Inputs/Output (SDA, SCL) High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage * High-Level Input Current Low-Level Input Current (pull-up) Low-Level Output Sink Current (SDA) Output Enable Input (OE) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) Clock Input (CLK_IN) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current VIH VIL II 2.0 VSS-0.3 -1 VDD+0.3 0.8 1 V V A VIH VIL IIH IIL VIH = 0.4V; VDD = 3.47V 2.0 VSS-0.3 -1 10 22 VDD+0.3 0.8 1 30 V V A A VIH VIL Vhys IIH IIL IOL Outputs low; VIH = 0.4V, VDD = 3.47V. Note: SDA requires an external pull-up to drive the data bus. VOL = 0.4V Outputs low Outputs low Outputs low 2.31 VSS-0.3 1.0 -1 5 10 11 25 1 15 VDD+0.3 0.9 V V V A A mA
Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current * Short Circuit Sink Current * IOH min IOH max IOL min IOL max zOH zOL IOZ IOSH IOSL VO = 0V; shorted for 30s, max. VO = 3.3V; shorted for 30s, max. VDD = 3.135V, VO = 2.0V VDD = 3.465V, VO = 3.135V VDD = 3.135V, VO = 1.0V VDD = 3.465V, VO = 0.4V VO = 0.5VDD; output driving high VO = 0.5VDD; output driving low 10 10 -5 -106 107 54 -54 -65 -28 69 33 17.9 16.3 53 24 24 5 -46 mA mA A mA mA
4.5.99
,62
10
)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
Table 10: AC Timing Specifications
Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical.
PARAMETER Overall Clock Skew, Maximum; SDRAM_0 to any SDRAM pin *
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK (MHz)
MIN.
TYP.
MAX.
UNITS
tskw tPLH(min) tPLH(max)
Measured on the rising edge at 1.5V; CL = 20pF Measured on the rising edge at 1.5V; CL = 20pF Measured on the rising edge at 1.5V; CL = 30pF Measured on the rising edge at 1.5V; CL = 20pF Measured on the rising edge at 1.5V; CL = 30pF
66.67 100 66.67 100 66.67 100 66.67 100 66.67 100
182 228 3.7 3.8 3.7 4.0 3.9 3.8 4.2 4.0
ps
Propagation Delay, Average; CLK_IN to any SDRAM pin * tPHL(min) tPHL(max)
ns
Clock Outputs (SDRAM_0:17 3.3V Type 4 Clock Buffer) tr(min) Rise Time * tr(max) tf(min) Fall Time * tf(max) tKH(min) Clock High Time * tKH(max) tKL(min) Clock Low Time * tKL(max) VO = 0.4V; CL = 30pF From rising edge to rising edge at 1.5V; CL = 20pF Duty Cycle * From rising edge to rising edge at 1.5V; CL = 30pF Tristate Enable Delay * Tristate Disable Delay * tPZL tPZH tPLZ tPHZ Output tristated to output active; CL = 20pF Output active to output tristated; CL = 20pF VO = 2.4V; CL = 30pF VO = 0.4V; CL = 20pF VO = 2.4V to 0.4V; CL = 30pF VO = 2.4V; CL = 20pF VO = 0.4V to 2.4V; CL = 30pF VO = 2.4V to 0.4V; CL = 20pF VO = 0.4V to 2.4V; CL = 20pF 66.67 100 66.67 100 66.67 100 66.67 100 66.67 100 66.67 100 66.67 100 66.67 100 66.67 100 66.67 100 1.0 0.9 1.2 1.0 1.0 0.7 1.1 0.8 6.5 3.8 6.5 3.8 6.5 4.6 6.3 4.5 49 45 50 46 4.7 4.6 6.3 7.9 ns ns % ns ns ns ns
4.5.99
,62
11
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X T
April 1999
Table 11: Serial Interface Timing Specifications
Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 from typical.
PARAMETER Clock frequency Bus free time between STOP and START Set up time, START (repeated) Hold time, START Set up time, data input Hold time, data input Output data valid from clock Rise time, data and clock Fall time, data and clock High time, clock Low time, clock Set up time, STOP
SYMBOL fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tAA tr tf tH tL tsu:STO SDA SDA SCL
CONDITIONS/DESCRIPTION
MIN. 10 4.7 4.7 4.0 250 300
MAX. 400
UNITS kHz s s s ns ns
Minimum delay to bridge undefined region of the falling edge of SCL to avoid unintended START or STOP SDA, SCL SDA, SCL SCL SCL 4.0 4.7 4.0
3.5 1000 300
s ns ns s s s
Figure 12: Bus Timing Data
~ ~
SCL
tsu:STA thd:STA tsu:STO
~ ~
SDA
~ ~
START
ADDRESS OR DATA VALID
DATA CAN CHANGE
STOP
Figure 13: Data Transfer Sequence
tf tH tr
~ ~
SCL
tL tsu:STA thd:STA thd:DAT tsu:DAT tsu:STO
~ ~
SDA IN
tAA tAA
tBUF
~ ~
SDA OUT
4.5.99
,62
12
)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
Figure 14: SDRAM_0:17 Clock Output (3.3V Type 4 Clock Buffer)
Voltage (V) 0 0.4 0.65 0.85 1 1.4 1.5 1.65 1.8 1.95 3.135 3.6 Low Drive Current (mA) MIN. 0 23 35 43 49 61 64 67 70 72 72 TYP. 0 34 52 65 74 93 98 103 108 112 112 112 MAX. 0 53 83 104 118 152 159 168 177 184 204 204 Voltage (V) 0 1 1.4 1.5 1.65 1.8 2 2.4 2.6 3.135 3.3 3.465 High Drive Current (mA)
220
MIN. -72 -72 -68 -67 -64 -60 -54 -39 -30 0
TYP. -116 -116 -110 -107 -103 -98 -90 -69 -56 -15 0
MAX. -198 -198 -188 -184 -177 -170 -157 -126 -107 -46 -23 0
6
200 180 160 140 120 100 80
60 A 40 r 20 0 8 -20 A -40 -60 P
0
0.5
1
1.5
2
2.5
3
3.5
4
-80
-100 -120 -140 -160 -180 -200 -220
PAWyhtrAW
MIN. TYP. MAX.
30 50 90
Figure 15: DC Measurement Points
3.3V VOH 3.3 = 2.4V 1.5V VOL 3.3 = 0.4V (device interface) VIL 3.3 = 0.8V
Figure 17: Timing Measurement Points
KP tr tKH tKL Duty Cycle
VDD
VIH 3.3 = 2.0V
tf
2.4V 1.5V 0.4V
(system interface)
Figure 16: Clock Skew Measurement Point
1.5V 3.3V
50%
50% VSS
50%
tskw
3.3V
10% tPLZ 90%
VOL tPZL VOH 50%
1.5V
tPHZ
tPHZ
4.5.99
,62
13
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X T
April 1999
6.0
Package Information
Table 12: 48-pin SSOP (7.5mm/0.300") Package Dimensions
DIMENSIONS INCHES MIN. A A1 A2 B C D E e H h L 0.095 0.008 0.088 0.008 0.005 0.620 0.292 0.400 0.010 0.024 0 MAX. 0.110 0.016 0.092 0.0135 0.010 0.630 0.299 0.410 0.016 0.040 8 MILLIMETERS MIN. 2.41 0.203 2.24 0.203 0.127 15.75 7.42 10.16 0.254 0.610 0 MAX. 2.79 0.406 2.34 0.343 0.254 16.00 7.59 10.41 0.410 1.02 8
BASE PLANE SEATING PLANE 1 ALL RADII: 0.005" TO 0.01"
AE"CAAC"#)#$E#AC
48
E
H
7 typ.
B
e
0.025 BSC
0.64 BSC
A2 D A1 A C L
Table 13: 48-pin SSOP (7.5mm/0.300") Package Characteristics
PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL JA L11 L12 C11 C12 CONDITIONS/DESCRIPTION Air flow = 0 m/s Center lead Center lead to any adjacent lead Center lead to VSS Center lead to any adjacent lead TYP. 93 3.3 1.6 0.6 0.2 UNITS C/W nH nH pF pF
4.5.99
,62
14
)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
Table 14: 28-pin SOIC (7.5mm/0.300") Package Dimensions
DIMENSIONS INCHES MIN. A A1 A2 B C D E e H h L 0.093 0.004 0.08 0.013 0.009 0.697 0.291 0.393 0.010 0.016 0 MAX. 0.104 0.012 0.100 0.013 0.009 0.713 0.299 0.419 0.030 0.05 8 MILLIMETERS MIN. 2.35 0.10 2.05 0.33 0.23 17.70 7.40 10.00 0.25 0.40 0 MAX. 2.65 0.30 2.55 0.51 0.32 18.10 7.60 10.65 0.75 1.27
BASE PLANE SEATING PLANE 1 ALL RADII: 0.005" TO 0.01"
AE"CAAC"#)#$E#AC
28
E
H
B
e
h x 45
7 typ.
0.05 BSC
1.27 BSC
A2 D A1 A C L
8
Table 15: 28-pin SOIC (7.5mm/0.300") Package Characteristics
PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL JA L11 L12 C11 C12 CONDITIONS/DESCRIPTION Air flow = 0 m/s Center lead Center lead to any adjacent lead Center lead to VSS Center lead to any adjacent lead TYP. 80 2.5 0.85 0.42 0.08 UNITS C/W nH nH pF pF
4.5.99
,62
15
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X T
April 1999
Table 16: 28-pin SSOP (5.3mm/0.209") Package Dimensions
DIMENSIONS INCHES MIN. A A1 A2 B C D E e H L 0.068 0.002 0.066 0.01 0.005 0.396 0.205 0.301 0.022 0 MAX. 0.078 0.008 0.07 0.015 0.008 0.407 0.212 0.311 0.037 8 MILLIMETERS MIN. 1.73 0.05 1.68 0.25 0.13 10.07 5.20 7.65 0.55 0 MAX. 2.00 0.21 1.78 0.38 0.20 10.33 5.38
1 ALL RADII: 0.005" TO 0.01"
AE"CAAC"#)#$E#AC
28
E
H
7 typ.
B
e
0.028 BSC
0.65 BSC 7.90 0.95 8
BASE PLANE
A2 D
SEATING PLANE
A
C L
A1
Table 17: 28-pin SSOP (5.3mm/0.209") Package Characteristics
PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL JA L11 L12 C11 C12 CONDITIONS/DESCRIPTION Air flow = 0 m/s Center lead Center lead to any adjacent lead Center lead to VSS Center lead to any adjacent lead TYP. 97 2.24 0.95 0.25 0.07 UNITS C/W nH nH pF pF
4.5.99
,62
16
)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999
7.0
Ordering Information
ORDERING CODE 11257-801 11257-811 11257-802 11257-812 PACKAGE TYPE 48-pin (7.5mm/0.300") SSOP 48-pin (7.5mm/0.300") SSOP 28-pin (7.5mm/0.300") SOIC 28-pin (7.5mm/0.209") SOIC 28-pin (5.3mm/0.209") SSOP 28-pin (5.3mm/0.209") SSOP 28-pin (7.5mm/0.300") SOIC 28-pin (7.5mm/0.300") SOIC 28-pin (7.5mm/0.300") SOIC 28-pin (7.5mm/0.300") SOIC OPERATING TEMPERATURE RANGE 0C to 70C (Commercial) 0C to 70C (Commercial) 0C to 70C (Commercial) 0C to 70C (Commercial) 0C to 70C (Commercial) 0C to 70C (Commercial) 0C to 70C (Commercial) 0C to 70C (Commercial) 0C to 70C (Commercial) 0C to 70C (Commercial) SHIPPING CONFIGURATION Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube
DEVICE NUMBER FS6050
FS6051
11257-806 11257-816
FS6053
11257-803 11257-813 11257-804 11257-814
FS6054
Purchase of I C components of American Microsystems, Inc., or one of its sublicensed Associated Companies conveys 2 2 a license under Philips I C Patent Rights to use these components in an I C system, provided that the system conforms 2 to the I C Standard Specification as defined by Philips.
2
Copyright (c) 1998 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com
4.5.99
,62
17
)6)6)6)6
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
X T
April 1999
8.0
8.1
Application Information
Reduction of EMI
Figure 18: Board Layout
CLK GND VOID
1 2 RS RS 1000pF RS RS 8 9 11 RS RS 1000pF RS RS 1000pF 17 18 32 31 41 40 38 4 5 48 47 45 44 RS RS 1000pF RS RS
MB GND
The primary concern when designing the board layout for this device is the reduction of electromagnetic interference (EMI) generated by the 18 copies of the 100MHz SDRAM clock. It is assumed the reader is familiar with basic transmission line theory.
8.1.1 Layout Guidelines To obtain the best performance, noise should be minimized on the power and ground supplies to the IC. Observe good high-speed board design practices, such as: Use multi-layer circuit boards with dedicated low impedance power and ground planes for the device (denoted as CLK VDD and CLK GND in Figure 18). The device power and ground planes should be completely isolated from the motherboard power and ground planes by a void in the power planes. Several low-pass filters using low impedance ferrite EHDGV DW 0+] DUH UHFRPPHQGHG WR GHFRuple the device power and ground planes from the motherboard power and ground planes (MB VDD and MB GND). The beads should span the gap between the power and ground planes. Seven beads for power and seven beads for ground are suggested (14 total) so that the clock rise times (1V/ns) can be maintained. Place 1000pF bypass capacitors as close as possible to the power pins of the IC. Use RF-quality lowinductance multi-layer ceramic chip capacitors. Six capacitors is optimal, one on each power/ground grouping as shown in Figure 18. Load similar clock outputs equally, and keep output loading as light as possible to help reduce clock skew and power dissipation. Use equal-length clock traces that are as short as possible. Rounded trace corners help reduce reflections and ringing in the clock signal. The clock traces must never cross the void area between power/ground planes. Each trace must have a complete plane (either VDD or GND) under the complete length of the trace.
13 14
36 35
RS RS 1000pF RS RS 1000pF
RS
21
28
RS
24
25
MB VDD CLK VDD
Component Layer MB GND MB VDD CLK GND CLK VDD Signal Layer MB GND MB VDD
8.1.2 Output Driver Termination A signal reflection will occur at any point on a PC-board trace where impedance mismatches exist. Reflections cause several undesirable effects in high-speed applications, such as an increase in clock jitter and a rise in electromagnetic emissions from the board. Using a properly designed series termination on each high-speed line can alleviate these problems by eliminating signal reflections.
Figure 19: Series Termination
zO DRIVER RS LINE zL
RECEIVE
4.5.99
,62
18
)6)6)6)6
X T
/RZ6NHZ &ORFN )DQRXW %XIIHU ,&V
April 1999 Series termination adds no dc loading to the driver, and requires less power than other resistive termination methods. Further, no extra impedance exists from the signal line to a reference voltage, such as ground. As shown in Figure 19, the sum of the driver's output impedance (zO) and the series termination resistance (RS) must equal the line impedance (zL). That is, pacitance, and the number of connected devices with their associated input currents. Control of the clock and data lines is done through open drain/collector current-sink outputs, and thus requires external pull-up resistors on both lines. A guideline is
RS = z L - zO .
Note that when the source impedance (zO+RS) is matched to the line impedance, then by voltage division the incident wave amplitude is one-half of the full signal amplitude.
RP <
tr , 2 x Cbus
Vi = V
( z O + RS ) V = ( z O + RS ) + z L 2
where tr is the maximum rise time (minus some margin) 2 and Cbus is the total bus capacitance. Assuming an I C 2 device on each DIMM, an I C controller, the clock buffer, and two other bus devices results in values in the 5k to 7k range. Use of a series resistor to provide protection against high voltage spikes on the bus will alter the values for RP.
The full signal amplitude may take up to twice as long as the propagation delay of the line to develop, reducing noise immunity during the half-amplitude period. Note also that the voltage at the receive end must add up to a signal amplitude that meets the receiver switching thresholds. The slew rate of the signal is also reduced due to the additional RC delay of the load capacitance and the line impedance. Also note that the output driver impedance will vary slightly with the output logic state (high or low).
Figure 20: Connections to the Serial Bus
SDA SCL
(optional)
RP
RP
RS
(optional)
RS
(optional)
RS
(optional)
RS
Data In Clock Out Data Out Clock In
Data In
Data Out
8.2
Dynamic Power Dissipation
TRANSMITTER
RECEIVER
High-speed clock drivers require careful attention to power dissipation. Transient power (PT) consumption can be derived from
PT = VDD x C load x f CLK x N SW
2
where Cload is the load capacitance, VDD is the supply voltage, fCLK is the clock frequency, and Nsw is the number of switching outputs. The internal heat (junction temperature, TJ) generated by the power dissipation can be calculated from
TJ = JA x PT + TA
where JA is the package thermal resistance, TA is the ambient temperature, and PT is derived above.
8.3.1 For More Information More detailed information on serial bus design can be 2 obtained from SMBus and I C Bus Design, available from the Intel Corporation at http://www.intel.com. 2 Information on the I C-bus can be found in the document 2 The I C-bus And How To Use It (Including Specifications), available from Philips Semiconductors at http://www-us2.semiconductors.philips.com. Additional information on the System Management Bus can be found in the System Management Bus Specification, available from the Smart Battery System Implementers' Forum at http://www.sbs-forum.org.
8.3
Serial Communications
Connection of devices to a standard-mode implementa2 tion of either the I C-bus or the SMBus is similar to that shown in Figure 20. Selection of the pull-up resistors (RP) and the optional series resistors (RS) on the SDA and SCL lines depends on the supply voltage, the bus ca4.5.99
,62
19

▲Up To Search▲

Price & Availability of 11257-811

	To Download 11257-811 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .